1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a multi-bit test circuit of a semiconductor apparatus.
2. Related Art
In the development and mass production of a semiconductor apparatus, various tests are performed for the semiconductor apparatus so as to verify the characteristics and functions of a product required in a specification, check performance of desired functions upon mounting and secure margins required in the specification, thereby improving the quality of the product.
In general, whether to pass or fail a product is determined based on the decision of a tester. That is to say, the tester generates control signals including a command, an address and a test data pattern in a sequence programmed by an engineer, applies the control signals to a product, and operates the product.
For example, address test data is written in a semiconductor apparatus, and data stored in the same address is read and outputted through a pad, so that whether to pass or fail a product is determined through comparing the data with a test pattern, the corresponding address is memorized, and an appropriate repair process may be performed for a failed address.
As a method of such a test, a multi-bit test or a parallel test is widely known in the art. In the multi-bit test, after a plurality of banks are simultaneously activated, read or write operations are performed so that a test time may be reduced. However, as the plurality of banks are simultaneously activated in the multi-bit test, a peak current markedly increases, and a fail is likely to occur due to noise caused by the peak current.